Possible Intel Arrow Lake-S Desktop CPU Die Layout Revealed, Rearranged Lion Cove P-Cores & Skymont E-Cores

Intel’s Arrow Lake-S Desktop CPU’s possible die layout has been revealed, giving us a first look at the restructured P-Core & E-Core arrangement.

Intel’s Arrow Lake-S Desktop CPU Dies To Feature A Vastly Rearranged Core Structure, Lion Cove P-Cores & Skymont E-Core Clusters Packed Tightly Together

It looks like Intel is making a lot of changes to the internal structure of its next-generation Arrow Lake CPUs. According to a block diagram shared by @Kepler_L2, it looks like the P-Cores and the E-Cores will be arranged tightly this time.

ARL-S looks something like this? pic.twitter.com/WnOr2QR43K

— Kepler (@Kepler_L2) January 18, 2024

Starting with the details, the diagram is based on information that was revealed almost a year ago and earlier this year, a possible render was brought up by Kepler which was followed up by Bionic Squash who stated that the compute tile would look a lot like the new layout. The Arrow Lake CPUs will feature up to 8 P-Cores based on the Lion Cove core architecture and 16 E-Cores based on the Skymont E-Core architecture. This will enable up to 24 cores and 24 threads since the CPUs are said to lack hyper-threading support.

The Intel Lion Cove P-Cores for Lunar Lake CPUs feature 2.5 MB L2 per core but Arrow Lake CPUs will feature 3.0 MB L2 cache per core and 3 MB of L3 cache for a total of 24 MB L3 that will be fully shared while the Skymont E-Cores will feature 4 MB of L2 cache per cluster and each cluster will be getting 3 MB of L3 cache.

• Arrow Lake P-Core Cache (Lion Cove): 3 MB L2 / 3 MB L3
• Arrow Lake E-Core Cache (Skymont): 4 MB L2 / 3 MB L3
• Raptor Lake P-Core Cache (Raptor Cove): 2 MB L2 / 3 MB L3
• Raptor Lake E-Core Cache (Gracemont): 4 MB L2 / 3 MB L3

The interesting part is that each two Lion Cove P-Cores will have an E-Core cluster stacked right in the middle & they won’t be separated from the P-Cores like in previous designs. This new layout might help in improving the inter-chip communication which can help the Thread Director decide better about which cores it can utilize better for the workload and can also help with Latencies on the same ring bus interconnect.

The travel time will also be reduced since the E-Cores were usually at the very end of the die which meant that the first P-Core communicated with the first E-Core by having to travel between the rest of the cores but having one E-Core cluster next to each of the P-Core can ultimately resolve a lot of intercommunication drawbacks encountered with Alder Lake & Raptor Lake chips. Intel already confirmed that the Lion Cove P-Core going into Lunar Lake and Arrow Lake CPUs are different in a lot of aspects.

For Lunar Lake, the Thread Director starts at E-Cores but for high-performance options, it will start at the P-Cores and give OEMs the flexibility to adjust the scheduling as per their need. Thread Direction provides the hint on which core to put the workload at, the ultimate decision rests at OS.

This is surely going to be an interesting design choice by Intel for its next-gen high-performance Arrow Lake CPUs. The architecture will scale across desktop and mobile form factors and will be coming first to the desktop space by October so stay tuned for more information in the coming months.

News Source: TechPowerUp